ÎÎInput Clock Frequency up to 6 GHz Typical ÎÎ4 pairs of differential LVPECL outputs ÎÎLow additive jitter, < 0.05ps (max) ÎÎInput CLK accepts: LVPECL, LVDS, CML, SSTL in.

such as providing fanout for low noise Pericom oscillators. Block Diagram Pin Configuration Q0Q0+ VDD GND REF_IN+ VT.

The PI6C5916004 is a high-performance low-skew 1-to-4 LVPECL fanout buffer. The CLK inputs accept LVPECL, LVDS, CML and SSTL signals. PI6C5916004 is ideal for clock distribution applications such as providing fanout for low noise Pericom oscillators..

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